Switching power supply circuit

ABSTRACT

A switching power supply circuit is protected from degradation and breakage of a MOS transistor when the inductive load is short-circuited or overloaded. To do this, the magnitude of the load current flowing through the MOS transistor is detected by a differential amplifier as a voltage drop due to the on resistance of the MOS transistor, a first latch circuit is set by the detection output of the differential amplifier generated when the voltage drop exceeds a predetermined value, and the first latch circuit is reset by the output of a control signal generating circuit controlling the MOS transistor. Current supplies from two constant current sources are switched between in accordance with the output of the first latch circuit to charge and discharge a capacitor for timer time setting. Then, the charging voltage of the capacitor is detected by a comparator, and a second latch circuit is set by the output of the comparator generated when the charging voltage exceeds a predetermined value. Then, the supply of a control signal from the control signal generating circuit to the MOS transistor is inhibited by the output of the second latch circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a switching power supply circuit, andmore particularly, to a switching power supply circuit having anovercurrent detecting function and an output short circuit detectingfunction.

Moreover, the present invention relates to a switching power supplycircuit capable of protection against degradation and breakage, due toan overcurrent or a short circuit current, of a switching element and aninductive load circuit and the like fed by the switching element.

2. Description of the Prior Art

In recent years, the need for protection against degradation andbreakage of parts under abnormal conditions has been increasing withdecrease in voltage and increase in current in semiconductor integratedcircuits.

Referring now to FIG. 3, a conventional switching power supply circuitwill be described.

The conventional switching power supply circuit comprises as shown inFIG. 3: an error amplifier 18 detecting the voltage at an outputterminal Vout; a switching element 19 whose on/off is controlled by theoutput of the error amplifier 18; a constant current source 20; acapacitor 21 charged by the constant current source 20; a comparator 22detecting the charging voltage of the capacitor 21; a latch circuit 23receiving as an input the output signal of the comparator 22; anactivating circuit 26 resetting the latch circuit 23; a control signalgenerating circuit 24; an AND circuit 25 serving as an output drivecircuit; a MOS transistor M2 serving as a switching element; a chokecoil 29; a Schottky diode 30; resistors 31 and 32 for output voltagedetection; and a capacitor 33 for output smoothing. Reference numeral 27represents a direct-current power supply terminal. Reference numeral 28represents a direct-current power source. The choke coil 29, theSchottky diode 30, the output voltage detecting resistors 31 and 32 andthe output smoothing capacitor 33 constitute an inductive load circuit.

The operation of the switching power supply circuit structured asdescribed above will be described.

Under normal operation conditions, the MOS transistor M2 is switched onand off by a pulse width modulation signal generated by the controlsignal generating circuit 24 in accordance with the voltage at theoutput terminal Vout. When the MOS transistor M2 is on, electric power,or energy is supplied from the direct-current power source 28 to thechoke coil 29, the capacitor 33 and the output load. At this time,energy is stored in the choke coil 29. When the MOS transistor M2 isswitched off by the pulse width modulation signal, a counterelectromotive force is caused at the choke coil 29, so that aregenerative current flows through the Schottky diode 30. By smoothingby the capacitor 33 the voltage caused at the choke coil 29 at thistime, a direct-current voltage is obtained. The direct-current voltageis output to the output terminal Vout.

The control signal generating circuit 24 generally includes a triangularwave generator (not shown) and an error comparator (not shown). Theerror comparator monitors the normally output voltage, or the voltage atthe output terminal Vout and compares the voltage with the output signalof the triangular wave generator, thereby generating the pulse widthmodulation signal whose pulse width varies according to the voltage atthe output terminal Vout. However, since this is not the essence of theinvention, description thereof is omitted.

When the inductive load circuit is overloaded or the output terminalVout is short-circuited under abnormal conditions, the output voltagedetecting error amplifier 18 detects that the potential at the outputterminal Vout is decreased, and outputs a high level, thereby switchingoff the switching element 19. At the same time, the charging of thecapacitor 21 is started by the constant current source 20. Thisoperation is maintained during a period for which the voltage at theoutput terminal Vout is lower than a predetermined voltage and the erroramplifier 18 is generating an inversion signal. During this period, thecharging of the capacitor 21 is continued, and when a predetermined timedetermined by the current value of the constant current source 20 andthe capacitance value of the capacitor 21 elapses and the chargingvoltage of the capacitor 21 exceeds a reference voltage Vx of thecomparator 22, the comparator 22 sets the latch circuit 23 and switchesoff the MOS transistor M2. By doing this, the MOS transistor M2 andparts of the inductive load circuit and the like are protected frombreakage or degradation.

In the above-described conventional structure, when the output of theswitching power supply circuit is overloaded or short-circuited todecrease the voltage at the output terminal Vout, a protection functionof causing the MOS transistor M2 to be off for a predetermined period oftime works. However, in the overloaded or the short-circuited condition,since no current limitation is imposed, an unlimited overcurrentcontinuously flows through the MOS transistor M2 and the inductive loadcircuit, or the choke coil 29, the Schottky diode 30, the resistors 31and 32 and the capacitor 33 from the start of the timer to the settingof the latch circuit 23. As a result, there is a possibility that theMOS transistor M2 or the inductive load circuit is degraded or brokendown.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a switching powersupply circuit capable of protecting the switching element and the partsconstituting the inductive load circuit with higher reliability.

A switching power supply circuit of the present invention comprises: adirect-current power source; an inductive load circuit supplied withelectric power from the direct-current power source; a switching elementinterrupting the electric power supplied from the direct-current powersource to the inductive load circuit; a control signal generatingcircuit generating a control signal periodically bringing the switchingelement into conduction; an overload detecting circuit generating anoverload detection signal when a load current flowing through theswitching element exceeds a predetermined current value; a first latchcircuit being set by the overload detection signal and being reset inresponse to a leading edge of the control signal; a timer circuitperforming a clocking operation during a period for which the firstlatch circuit is set, and generating a time-up signal when apredetermined clocking period elapses; a second latch circuit being setin response to the time-up signal of the timer circuit; and an outputdrive circuit receiving as inputs the control signal and output signalsof the first and the second latch circuits, bringing the switchingelement into conduction in response to the control signal under normalconditions, and shutting off the switching element irrespective of thecontrol signal when at least one of the first and the second latchcircuits is set.

According to this structure, the overload detection signal is generatedwhen the load current flowing through the switching element exceeds thepredetermined current value, and at this time, the switching element isshut off irrespective of the presence or absence of the control signal,so that the on period of the switching element is reduced. Consequently,the maximum current value can be limited to not more than apredetermined value. Further, at the time of the occurrence of anabnormal current when the overloaded condition continues, the control ofthe switching element can be stopped so that the switching element isheld in the shut-off condition. Consequently, the protection againstdegradation and breakage of the switching element and parts of theinductive load circuit can be made more reliable.

In the switching power supply circuit having the above-descriedstructure, for example, it is preferable that the overload detectingcircuit compares an on voltage of the switching element with apredetermined first reference voltage in synchronism with switching onof the switching element to thereby detect that the load current flowingthrough the switching element exceeds the predetermined current value.

According to this structure, since the overcurrent or the output shortcircuit current is detected by using the on resistance of the switchingelement, no special current detecting resistor is necessary.Consequently, only a small number of parts are required, and since thereis no power loss at the current detecting resistor, the power source useefficiency never decreases.

In the switching power supply circuit having the above-describedstructure, for example, the timer circuit comprises: a capacitor;charging means for passing a charging current through the capacitorduring the period for which the first latch circuit is set; dischargingmeans for passing a discharging current through the capacitor during aperiod for which the first latch circuit is reset; and a comparatorcomparing a charging voltage of the capacitor with a predeterminedsecond reference voltage and outputting the time-up signal when thecharging voltage of the capacitor exceeds the second reference voltage.

According to this structure, when it is detected that the load currentof the switching element becomes an overcurrent, that is, that theswitching element is in the overloaded condition, the charging of thecapacitor is started, and the clocking operation is performed while thesucceeding charging and discharging of the capacitor are repeated, sothat the time-up period that lasts until the charging voltage of thecapacitor reaches the second reference voltage is longer than that ofthe conventional example. Consequently, the capacitance value of thecapacitor can be made lower that that of the conventional structure.That is, the time-up period can be made long although the capacitancevalue of the capacitor is low. Consequently, the capacitor can be formedso as to be small, and this enables the timer circuit including thecapacitor to be integrated into a semiconductor integrated circuit.

Moreover, it is preferable that in the timer circuit comprising thecapacitor, the charging means, the discharging means and the comparator,a level of the second reference voltage is set so that a period fromstart of a charging and a discharging operation to generation of thetime-up signal, that is, a time-up period is not less than twice aperiod of the control signal. Further, it is more preferable that theperiod is three to five times a period of the control signal

According to this structure, even when the capacitor is charged as aresult of a one-shot noise intruding from a peripheral circuit or aperipheral apparatus to cause the first latch circuit to malfunction,the discharging means functions to discharge the capacitor so that thecharging voltage decreases. Consequently, even when a one-shot noiseintrudes from a peripheral circuit or a peripheral apparatus, it isavoided that the operation of the switching element is stopped by amalfunction due to the noise, so that a highly reliable overcurrentdetecting operation can be performed.

Moreover, it is preferable that in a switching power supply circuitcomprising the timer circuit comprising the capacitor, the chargingmeans, the discharging means and the comparator, the following arefurther provided: an activating circuit a period of generation of whichoutput signal is set to a period longer than a period of the controlsignal; and short-circuiting means for short-circuiting across thecapacitor in response to the setting of the second latch circuit, andthe second latch circuit is periodically reset by an activation signalof the activating circuit.

According to this structure, when an operator in charge of operating anelectronic apparatus provided with the switching power supply circuit ofthe present invention makes a mistake in the operation of the apparatusto short-circuit the inductive load circuit, not only the overloadedcondition is detected and the switching element is shut off to therebyprotect the circuit but also the shut-off condition can be periodicallycanceled. Consequently, by the operator eliminating the short-circuitedcondition, the overcurrent detection operation for causing theprotection operation to function is resumed and the primary function ofthe switching power supply circuit can be delivered.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the structure of a switching powersupply circuit according to an embodiment of the present invention;

FIG. 2 is a timing chart showing the operation timing of the switchingpower supply circuit according to the embodiment of the presentinvention; and

FIG. 3 is a circuit diagram showing the structure of the conventionalswitching power supply circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

An embodiment of the present invention will be described with referenceto the drawings.

FIG. 1 shows the structure of a switching power supply circuit accordingto the embodiment of the present invention.

In FIG. 1, reference designation M1 represents a MOS transistor as anexample of a switching element supplying electric power to an inductiveload circuit.

Reference numeral 1 represents a differential amplifier detecting thevoltage across the MOS transistor M1.

Reference numeral 2 represents a latch circuit being set by receivingthe output signal of the differential amplifier 1.

Reference numeral 3 represents a comparator. Reference numeral 4represents a latch circuit being set by receiving the output of thecomparator 3.

Reference numerals 5 and 6 represent AND circuits.

Reference numerals 7 and 8 represent constant current sources.

Reference numerals 9 and 10 represent switching elements.

Reference numeral 11 represents a capacitor for timer time setting.Reference numeral 12 represents a direct-current power supply terminal.

Reference numerals 13 and 14 represent inverter circuits.

Reference numeral 15 represents an activating circuit resetting thelatch circuit 4.

Reference numeral 16 represents a control signal generating circuit.

Reference numeral 17 represents a switching element as short-circuitingmeans.

Reference numeral 28 represents a direct-current power source supplyingelectric power.

Reference numeral 29 represents a choke coil.

Reference numeral 30 represents a Schottky diode.

Reference numeral 33 represents a capacitor for smoothing.

Reference designation Vout represents an output terminal outputting asmoothed direct-current output voltage.

The choke coil 29, the Schottky diode 30 and the capacitor 33 constitutean inductive load circuit for the MOS transistor M1. This inductive loadcircuit is supplied with electric power by the direct-current powersource 28. The supply of the electric power is interrupted by the MOStransistor M1. When the MOS transistor M1 performs the interruptingoperation, an induced voltage occurs across the choke coil 29. Theinduced voltage is converted into a direct-current output voltage bybeing smoothed by the capacitor 33, and the direct-current outputvoltage is output from the output terminal Vout.

The control signal generating circuit 16 generates a control signal forperiodically bringing the MOS transistor M1 into conduction,specifically, a pulse width modulation signal. Under normal operationconditions, this control signal is applied to the gate of the MOStransistor M1 through the AND circuit 6 serving as the output drivecircuit, thereby controlling the on/off, or the switching of the MOStransistor M1.

The AND circuit 6 serving as the output drive circuit receives as inputsthe control signal output from the control signal generating circuit 16and the output signals of the first and the second latch circuits 2 and4. With this, in normal times, the MOS transistor M1 is brought intoconduction in accordance with the control signal output from the controlsignal generating circuit 16, and when at least one of the first and thesecond latch circuits 2 and 4 is set, the MOS transistor M1 is shut offirrespective of the control signal.

The MOS transistor M1 shown in FIG. 1 is connected, specifically, asbeing an N-channel MOS transistor. That is, FIG. 1 shows a circuitexample in which the drain of the MOS transistor M1 is connected to thedirect-current power source 28, the gate thereof is connected to theoutput of the AND circuit 6 and the inductive load circuit is driven asa source follower type. It is considered that the MOS transistor M1, orthe N-channel MOS transistor is brought into complete conduction when ahigh level is input from the AND circuit 6.

When the degree of conduction of the N-channel MOS transistor is low,the AND circuit 6 is operated at a power supply voltage increased by abootstrap circuit (not shown) to thereby increase the amplitude of thecontrol signal applied to the gate.

As the MOS transistor M1, a P-channel MOS transistor is also usable. Inthat case, the source of the MOS transistor M1 is connected to thedirect-current power source 28, an inverter circuit (not shown) isprovided at the output end of the AND circuit 6, the inversion signal ofthe output signal of the AND circuit 6 is applied to the gate, and theinductive load is driven as a source grounded type.

The minimum function as a switching power supply circuit is implementedby the control signal generating circuit 16, the MOS transistor M1, theSchottky diode 30, the choke coil 29 and the capacitor 33. That is, whenthe MOS transistor M1 is brought into conduction in accordance with thepulse width of the control signal output from the control signalgenerating circuit 16, energy is stored in the choke coil 29 by theconduction operation, and the induced voltage induced by the choke coil29 is converted into a direct-current output voltage by being smoothedby the capacitor 33. Since this direct-current output voltage variesaccording to the pulse width, a predetermined direct-current outputvoltage can be output by controlling the switching of the MOS transistorM1 with a predetermined pulse width.

However, since the direct-current output voltage tends to vary also byvariations in load current, when it is intended to stabilize thedirect-current output voltage against load variations, an errorcomparator (not shown) performing error comparison between the voltageat the output terminal Vout and a reference voltage is provided, afeedback path for feeding back the error comparison output of the errorcomparator to the control signal generating circuit 16 is formed, andthe pulse width of the control signal is varied according to the outputof the error comparator. By doing this, the direct-current outputvoltage can be stabilized.

An overload detecting circuit comprises: the differential amplifier 1comparing the on voltage of the MOS transistor M1 with a first referencevoltage generated from a reference voltage generator V1; and the ANDcircuit 5 receiving as inputs the output of the differential amplifier 1and the control signal of the control signal generating circuit 16.

Now, a current detecting method using the on resistance of the MOStransistor will be described. When the MOS transistor is brought intocomplete conduction, the impedance between the drain and the source ofthe MOS transistor exhibits a characteristic substantially equal to aresistor, and when the drain current increases, the drain-source voltage(on voltage) increases substantially in proportion thereto. Therefore,if the on voltage can be detected in synchronism with the switching onof the MOS transistor, the current flowing through the MOS transistorcan be detected.

Conventionally, to precisely detect the operating current of a switchingelement, a pure resistor is connected in series to the MOS transistor M1and the voltage across the resistor is detected being converted into acurrent value. Compared to this conventional current detecting method,in the current detecting means used by the present invention, that is,the current detection by the on resistance of the MOS transistor,although the current detection precision is inferior, no problem iscaused in uses such as the detection of the overloaded condition or theshort circuit condition of the output. The overload detecting circuitutilizing the above-described current detecting method will bedescribed.

In the overload detecting circuit, the AND circuit 5 is connected to theoutput end of the differential amplifier 1. Since the MOS transistor M1is conducting when the control signal is high, the output signal fromthe differential amplifier 1 is made effective only when the controlsignal which is high is input to the input of the AND circuit 5. Withthis, the on voltage of the MOS transistor M1 is compared with the firstreference voltage of the reference voltage generator V1 by thedifferential amplifier 1 in synchronism with the switching on of the MOStransistor M1. The differential amplifier 1 generates an output signal,or an overcurrent detection signal when the load current flowing throughthe MOS transistor M1 exceeds a predetermined current value. With thisoverload detecting circuit, since no special current detecting resistoris necessary, only a small number of parts are required and since thereis no power loss at the current detecting resistor, the power source useefficiency never decreases.

The first latch circuit 2 is set by an overcurrent detection signalwhich is the output signal of the AND circuit 5, is reset in response tothe leading edge of the control signal of the control signal generatingcircuit 16, in this example, the rising edge of the control signal, andcontrols the circuit operation of the timer circuit by its own Q output.While the control signal generating circuit 16 is designed based on thepositive logic where the high level is effective, when it is designedbased on the negative logic where low level is effective, the leadingedge of the control signal is the falling edge of the control signal.

The timer circuit comprises the constant current sources 7 and 8, thetimer time setting capacitor 11, the switching elements 9 and 10, theinverter circuit 13 and the comparator 3.

The constant current source 7 and the switching element 9 constitutecharging means for passing a charging current through the capacitor 11,and each comprise a transistor. The transistor constituting the constantcurrent source 7 is capable of driving the switching of its own constantcurrent operation. Shutting off a transistor constituting the constantcurrent circuit 8 in accordance with the Q output of the latch circuit 2makes it unnecessary to provide the switching element 9.

The constant current source 8 and the switching element 10 constitutedischarging means for passing a discharging current through thecapacitor 11, and each comprise a transistor. Driving the switching ofthe transistor constituting the constant current source 8 and shuttingoff the transistor in accordance with the output of the inverter circuit13 makes it unnecessary to provide the switching element 10.

Since the switching element 9 is brought into conduction in accordancewith the Q output of the latch circuit 2 and the switching element 10 isbrought into conduction in accordance with the inversion signal of the Qoutput of the latch circuit 2 produced by the inverter circuit 13, whenthe charging means functions, the discharging means is shut off, andwhen the discharging means functions, the charging means is shut off.

Now, the relationship between the set value of the discharging currentand the set value of the charging current will be described. To reducethe capacitance value of the capacitor 11, the level of the dischargingcurrent is set to be the same as or not more than twice that of thecharging current. However, since the impedance of the capacitor 11increases, the circuit is susceptible to noises that come flying, andthe comparator 3 tends to malfunction. When the reliability of thecircuit operation is emphasized, the value of the discharging current isset to a value between zero and half the charging current and thecapacitance value of the capacitor 11 is set to a rather high value.

In the charging and the discharging means constituted by the constantcurrent sources 7 and 8 and the switching elements 9 and 10, that is,the charging means and the discharging means, when the latch circuit 2is set by the overcurrent detection signal, the switching element 9operating on the Q output of the latch circuit 2 is brought intoconduction, and a charging operation of passing the charging currentthrough the capacitor 11 is performed. When the latch circuit 2 is resetby the control signal of the control signal generating circuit 16, theswitching element 10 operating on the output of the inverter circuit 13is brought into conduction, and a discharging operation of passing thedischarging current through the capacitor 11 is performed.

Since the timer circuit performs a clocking operation of graduallycharging the capacitor 11 while repeating the charging operation and thedischarging operation, a time-up period that lasts until the chargingvoltage reaches a second reference voltage V2 is longer than that of theconventional structure, so that the capacitance value of the capacitor11 can be reduced. Consequently, the capacitor 11 can be formed so as tobe small, and this enables the timer circuit including the capacitor 11to be integrated into a semiconductor integrated circuit.

The comparator 3 constituting part of the timer circuit compares thecharging voltage of the capacitor 11 with the output voltage of thereference voltage generator V2, or the second reference voltage, andwhen the charging voltage of the capacitor 11 exceeds the secondreference voltage, outputs a time-up signal, or a high-level outputvoltage.

The level of the second reference voltage of the reference voltagegenerator V2 is set so that the period from the start of the chargingand the discharging operations by the charging and the discharging meansto the generation of the time-up signal, or the time-up period is notless than twice, preferably, three to five times the period of thecontrol signal of the control signal generating circuit 16. By doingthis, the time-up signal is not generated when the MOS transistor M1brought into conduction in accordance with the control signal of thecontrol signal generating circuit 16 is switched on only once, but isgenerated only when the MOS transistor M1 is continuously switched onseveral times.

Generally, it is highly likely that noises intrude from peripheralcircuits and peripheral apparatuses into switching power supply circuitsprovided in various electronic apparatuses and in various places inelectronic apparatuses. However, with the timer circuit having theabove-described structure, even if the first latch circuit 2malfunctions due to a one-shot noise and the capacitor 11 is charged bymistake, since by the latch circuit 2 being reset by the next controlsignal, the discharging means functions to discharge the charges in thecapacitor 11 and decrease the charging voltage, the time-up signal isnever output by one-shot noises, so that such malfunctions as to stopthe operation of the MOS transistor can be avoided. Consequently, highlyreliable overcurrent detection can be performed.

Now, the ground for the above-described setting of the time-up periodwill be described. Malfunctions due to one-shot noises that come flyingfrom peripheral apparatuses can be avoided by setting the time-up periodso as not to end after a single charging operation. To do this, thetime-up period is set so as to be not less than twice the period of thecontrol signal. When the time-up period is long, measures can be takenagainst malfunctions even when one-shot noises are intensively caused,and the longer the time-up period is, the more reliable the circuitoperation is. However, when the time-up period is long, the protectionfunction starts to operate late, which is undesirable. The practicaltime-up period is three to five times the period of the control signal.

Next, the circuit operation, particularly, the overcurrent detectingoperation of the switching power supply circuit structured as describedabove will be described in detail with reference to the timing chartshown in FIG. 2.

FIG. 2 is a timing chart showing, with the horizontal axis as time,operating waveforms of the parts represented by (a) to (e) in FIG. 1.The waveform (a) of FIG. 2 shows the control signal (pulse widthmodulation signal) generated by the control signal generating circuit16. The waveform (b) of FIG. 2 shows the terminal voltage of the MOStransistor M1. The waveform (c) of FIG. 2 is the output voltage of the Qoutput of the first latch circuit 2. The waveform (d) of FIG. 2 is theoutput voltage of the AND circuit 6 which is the output drive circuit.The waveform (e) of FIG. 2 shows the terminal voltage of the capacitor11.

In FIG. 2, a first period t1 shows the waveforms under normal operationconditions, that is, conditions where the circuit is operating on a loadcurrent of a normal level. During the period t1, a waveform the same asthe control signal of the control signal generating circuit 16 shown bythe waveform (a) is output as the waveform (d) from the output terminalof the AND circuit 6. When the control signal shown by the waveform (a)is high, the MOS transistor M1 is on, and the terminal voltage of theMOS transistor M1 at this time is of a high level which is slightlylower in potential than a power supply voltage Vcc as shown by thewaveform (b). The waveforms of the high-level parts of the terminalvoltage shown by the waveform (b) decline toward the right because of aninfluence of the counter electromotive force caused when the inductiveload circuit is switched.

Although the terminal voltage of the MOS transistor M1 shown by thewaveform (b) is compared by the differential amplifier 1 with areference potential lower than the power supply voltage Vcc byapproximately the first reference voltage of the reference voltagegenerator V1, since this terminal voltage does not decrease to thereference potential, the overcurrent detection signal is not output fromthe overload detecting circuit including the differential amplifier 1.Therefore, the latch circuit 2 is held being reset, and a low-levelvoltage is output from the Q output of the latch circuit 2 shown by thewaveform (c). For this reason, the succeeding timer circuit does notoperate, and the charging of the capacitor 11 is not performed.Consequently, the terminal voltage of the capacitor 11 is held low asshown by the waveform (e).

A second period t2 in FIG. 2 shows the waveforms in an overloadedcondition, that is, a condition where the load current is excessive.During the period t2, since the current flowing through the MOStransistor M1 is excessive, the on voltage of the MOS transistor M1 ishigh, so that the potential of the high-level parts of the terminalvoltage of the MOS transistor M1 is lower than that under the normaloperation conditions as shown by the waveform (b). The terminal voltageof the MOS transistor M1 declining toward the right decreases to thereference potential of (Vcc−V1) at an early point of time as shown bythe waveform (b). When the terminal voltage of the MOS transistor M1 isdecreased to the reference potential as shown by the waveform (b), thedifferential amplifier 1 outputs a high level, and a high-level signal,or the overcurrent detection signal is output from the output of the ANDcircuit 5, or the output of the overload detecting circuit.

Then, by the overcurrent detection signal being input to the set inputend of the first latch circuit 2, the latch circuit 2 is set, so that ahigh-level voltage is output from the Q output as shown by the waveform(c). During this high-level period of the Q output, or the period tc,the switching element 9 is conducting, and the charging operation ofpassing the charging current through the capacitor 11 from the constantcurrent source 7 is performed. That is, as shown by the waveform (a),the charging operation is started in response to the first controlsignal generated after the overloaded condition arises, and the chargingvoltage of the capacitor 11 shown by the waveform (e) increases.

Then, when the second control signal is input, the latch circuit 2 isreset, so that the discharging operation of passing the dischargingcurrent through the capacitor 11 is performed and the dischargingvoltage of the capacitor 11 decreases as shown by the waveform (e)(period td). When the overload detecting circuit is actuated while thesecond control signal is being input, the latch circuit 2 is set again,and the charging operation is resumed, so that the charging voltage ofthe capacitor 11 further increases as shown by the waveform (e). Theabove-described operation is performed every time the control signalbecomes high in the waveform (a), and the charging voltage shown by thewaveform (e) increases every time.

At this time, by the Q output of the latch circuit 2 being input to theAND circuit 6, the width of the high-level period of the waveform (d)output from the output terminal of the AND circuit 6 is made smallerthan the width of the high-level period of the control signal of thecontrol signal generating circuit 16 shown by the waveform (a).Consequently, the on period of the MOS transistor M1 is decreased, sothat the current flowing through the MOS transistor M1 is limited.

Then, when the charging voltage shown by the waveform (e) increases toreach the level of the second reference voltage of the reference voltagegenerator V2, the comparator 3 is actuated and outputs the time-upsignal. The second latch circuit 4 is set by the time-up signal, theoutput signal of the AND circuit 6 is fixed at a low level as shown bythe waveform (d), the switching element 17 operating on the output ofthe inverter circuit 14 is switched on, and the charges stored in thecapacitor 11 are discharged so that the charging voltage is made zero.

With the operations performed up to this point, the detecting operationof detecting that the load current flowing through the MOS transistor M1exceeds a predetermined current value is completed, and thereafter, theMOS transistor M1 continues to be off so that the MOS transistor M1 isshut off irrespective of the presence or absence of the control signalshown by the waveform (a).

In this manner, the maximum current value can be limited to not morethan a predetermined value, and further, at the time of the occurrenceof an abnormal current when the overloaded condition continues, thecontrol of the MOS transistor M1 can be stopped. Consequently, the MOStransistor M1 and parts of the inductive load circuit such as the chokecoil 29 can be protected against degradation and breakage with higherreliability.

However, with this structure, when the second latch circuit 4 is set,the MOS transistor M1 continues to be off. Consequently, the primaryfunction of the switching power supply circuit is not restored unlessthe power supply voltage supplied to the entire switching power supplycircuit is shut off. This problem can be solved by resetting the secondlatch circuit 4 by the output signal of the activating circuit 15.

Lastly, a method of effectively utilizing the activating circuit 15 willbe described.

When the time from the start of the charging operation to the generationof the time-up signal in the timer circuit is the time-up period, bysetting the period of generation of the output signal of the activatingcircuit 15 resetting the second latch circuit 4 to a period sufficientlylonger than the time-up period, the following advantage is produced:

When an operator in charge of operating an electronic apparatus providedwith the switching power supply circuit makes a mistake in the operationof the apparatus to short-circuit the inductive load circuit, not onlythe overloaded condition is detected and the MOS transistor M1 is shutoff for protection but also the shut-off condition can be periodicallycanceled. Consequently, by the operator eliminating the short-circuitedcondition, the overcurrent detection operation for causing theprotection operation to function is resumed and the primary function ofthe switching power supply circuit can be delivered.

What is claimed is:
 1. A switching power supply circuit comprising: a direct-current power source; an inductive load circuit supplied with electric power from said direct-current power source; a switching element interrupting the electric power supplied from said direct-current power source to said inductive load circuit; a control signal generating circuit generating a control signal periodically bringing said switching element into conduction; an overload detecting circuit generating an overload detection signal when a load current flowing through said switching element exceeds a predetermined current value; a first latch circuit being set by the overload detection signal and being reset in response to a leading edge of the control signal; a timer circuit performing a clocking operation during a period for which said first latch circuit is set, and generating a time-up signal when a predetermined clocking period elapses; a second latch circuit being set in response to the time-up signal of said timer circuit; and an output drive circuit receiving as inputs the control signal and output signals of said first and said second latch circuits, bringing said switching element into conduction in response to the control signal under normal conditions, and shutting off said switching element irrespective of the control signal when at least one of said first and said second latch circuits is set.
 2. A switching power supply circuit according to claim 1, wherein said overload detecting circuit compares an on voltage of said switching element with a predetermined first reference voltage in synchronism with switching on of said switching element to thereby detect that the load current flowing through said switching element exceeds the predetermined current value.
 3. A switching power supply circuit according to claim 1, wherein said timer circuit comprises: a capacitor; charging means for passing a charging current through said capacitor during the period for which said first latch circuit is set; discharging means for passing a discharging current through said capacitor during a period for which said first latch circuit is reset; and a comparator comparing a charging voltage of said capacitor with a predetermined second reference voltage and outputting the time-up signal when the charging voltage of said capacitor exceeds the second reference voltage.
 4. A switching power supply circuit according to claim 3, wherein in said timer circuit, a level of the second reference voltage is set so that a period from start of a charging and a discharging operation to generation of the time-up signal is not less than twice a period of the control signal.
 5. A switching power supply circuit according to claim 3, wherein in said timer circuit, a level of the second reference voltage is set so that a period from start of a charging and a discharging operation to generation of the time-up signal is three to five times a period of the control signal.
 6. A switching power supply circuit according to claim 3, comprising: an activating circuit a period of generation of which output signal is set to a period longer than a period of the control signal; and short-circuiting means for short-circuiting across said capacitor in response to the setting of said second latch circuit, wherein said second latch circuit is periodically reset by an activation signal of said activating circuit. 